Key Engineering Takeaways
- •Harvard Architecture uses SEPARATE physical memory buses for program code (Flash) and data variables (SRAM), allowing simultaneous fetch and data read.
- •Von Neumann Architecture shares a single unified bus for both program instructions and data, creating a potential throughput bottleneck (Von Neumann Bottleneck).
- •Almost all modern microcontrollers (ARM Cortex-M, AVR, RISC-V, Xtensa) are RISC (Reduced Instruction Set Computer) designs with simple, single-cycle instructions.
- •Direct Memory Access (DMA) controllers transfer data between ADC/UART and SRAM automatically without consuming CPU clock cycles.
Prerequisites
- • Fetch-Decode-Execute instruction cycle
Required Hardware / Tools
- • STM32 or ESP32 development board for architecture inspection
Memory Architectures: Von Neumann vs Harvard Architecture
How a microcontroller connects its CPU to memory determines its speed and throughput:
### 1. Von Neumann Architecture (Shared Bus)
In a Von Neumann system, program code and data share the exact same physical memory bus. The CPU cannot read a data variable from RAM at the same instant it fetches the next program instruction from ROM. This limitation is known as the **Von Neumann Bottleneck**.
### 2. Harvard Architecture (Separate Independent Buses)
In a Harvard Architecture, **Instruction Memory (Flash)** and **Data Memory (SRAM)** have dedicated, independent address and data buses. The CPU can fetch the next instruction from Flash over the I-Code bus while simultaneously reading sensor arrays from SRAM over the D-Code bus in the exact same clock cycle.
*Virtually all modern microcontrollers (ARM Cortex-M, AVR, PIC, ESP32) utilize modified Harvard architectures for maximum real-time performance.*
Instruction Set Design: RISC vs CISC
### RISC (Reduced Instruction Set Computer)
- **Philosophy**: Use a small set of highly optimized, uniform-length instructions where almost every instruction executes in **exactly one single clock cycle**.
- **Registers**: Large register bank (e.g. 16 to 32 general-purpose 32-bit registers).
- **Examples**: **ARM Cortex-M** (STM32, RP2040), **AVR** (Arduino ATmega), **RISC-V** (ESP32-C3/C6), **Xtensa** (ESP32).
### CISC (Complex Instruction Set Computer)
- **Philosophy**: Provide complex multi-step instructions that can perform arithmetic directly in memory across variable byte lengths and multiple clock cycles.
- **Examples**: Traditional desktop x86/x64 processors (Intel, AMD).
Frequently Asked Questions
What is Direct Memory Access (DMA)?
DMA is a dedicated hardware co-processor inside advanced 32-bit MCUs (STM32, ESP32). When high-speed sensors stream data (e.g., ADC audio or SPI camera frames at 20MB/s), DMA streams the bytes directly into SRAM memory buffers without interrupting the CPU, leaving the processor 100% free for control algorithms.
Tags:#Basic Microcontrollers#Harvard Architecture#Von Neumann#RISC#CISC#ARM Cortex#Peripherals