Key Engineering Takeaways
- •STM32 hardware timers feature built-in Quadrature Encoder Interface (SMS=001/010/011) that increments counter registers with zero CPU interrupts.
- •Center-aligned PWM reduces electromagnetic interference (EMI) and current harmonics on motor coils.
- •Configure Auto-Reload Registers (ARR) and Prescalers (PSC) for exact microsecond-level frequency synthesis.
Prerequisites
- • C pointers
- • ARM Cortex architecture basics
Hardware Quadrature Encoder Counter Mode (TIM_SMCR)
Instead of software pin interrupts that waste CPU cycles at high wheel RPMs, STM32 General-Purpose Timers (e.g., TIM2, TIM3, TIM4) contain dedicated digital decoder logic. The timer hardware decodes Channel 1 (TI1) and Channel 2 (TI2) automatically directly updating the `TIMx->CNT` register.
Tags:#STM32#Bare Metal#Timers#PWM#ARM Cortex#Registers